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April 2011 Issue |
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Welcome to the April issue of eEuronews!
| For the last 6 years, every editorial of the April issue is dedicated to the upcoming CDNLive! EMEA user conference. With CDNLive! EMEA we created a unique opportunity for all our users and partners to get together |
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once a year and to be inspired to outperform in electronic design.
This year's conference will focus on new technologies and methodologies to realize advanced silicon, SoCs, and systems in alignment with the EDA360 vision. The agenda is now complete and all details about the event including the registration site are available on our homepage.
The registration number is increasing day by day, and for the Designer Expo, we have reached a record number of exhibitors.
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To give you a first glance at the new location and what to expect, Alexander Duesener, head of the Cadence EMEA field Organization and I met up at the Dolce Hotel in |
Munich. Take a look at the short video and get inspired to attend the event.
To stay up-to-date on the latest news and information on CDNLive! view videos and download documents on our CDNLive! Multimedia Channel.
See you in May,
Wolfgang Stronski
Marketing Director EMEA, Cadence |
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| System Design and Verification |
User View: Why and How to Use Transaction-Based Acceleration
By Richard Goering
Transaction-based acceleration can speed up simulation hundreds of times, but you need to develop a good strategy to take full advantage of it, according to a paper authored by Cadence and Broadcom and presented at the recent DVCon conference. The paper detailed Broadcom's experience using transaction-based acceleration with the Cadence Palladium hardware verification platform. The paper was titled "Transaction-Based Acceleration - Strong Ammunition in Any Verification Arsenal." It was presented by Chandrasekhar Poorna, principal engineer at Broadcom. Some quick background: With simulation acceleration, the design under test (DUT) is synthesized into hardware while a simulation testbench runs on a workstation. While basic acceleration traditionally involves a signal-level interface between the software running the testbench and the hardware acceleration platform, transaction-based acceleration brings this interface up to the transaction level, greatly reducing communication overhead and improving performance even further.
Read More »
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| Logic Design |
Cadence blog: A Look Behind the Si2 CPF 2.0 Release
The long awaited new version of the Common Power Format, CPF 2.0, was released by the Silicon Integration Initiative (Si2), an industry standards organization, on the 15th February 2011. Here are several interesting observations from this latest release.
First of all, this new release is a big step forward for interoperability between IEEE 1801 (Unified Power Format 2.0), the other industry power intent format, and CPF. In 2009 the format working group of the Si2 Low Power Coalition (LPC), which is responsible for maintaining CPF, released a document called Interoperability Guide for Power Format Standards, which describes clearly how to map between an IEEE 1801 command/option to a CPF counterpart. It also shows which commands/options of 1801 are declared as non-interoperable due to missing constructs in CPF and the methodology differences between the two formats.
Read More »
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| Functional Verification |
Cadence Incisive Specman and Enterprise Manager help Siemens Drive Technologies ASIC Design Team Stay on Schedule with a Metric-Driven Verification Methodology
Siemens achieves aggressive quality goals and finishes project ahead of schedule using Cadence metric-driven verification technologie.
Recently, the Siemens ASIC design team embarked upon a critical new project that involved changing existing modules to develop an ARM-based system-on-chip (SoC) solution for encoder applications. The team faced several verification challenges right from the start-they had to meet aggressive targets for both quality and timeline while also building an all-encompassing chip-level verification plan that covered both hardware and software features and addressed real-life use cases.
Read More »
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| Custom IC Design |
On March 14, Cadence announced the new custom/analog design flow.
Among enhancements to publishing and design-checking software and next-generation waveform viewing, the Cadence custom/analog flow is fortified by three key integrated components: a flow for parasitic-aware design, a new "in-design" manufacturing signoff tool (Virtuoso DFM), and a new power and signal integrity management tool (Virtuoso Power System).
Click here for all the details »
Virtuoso Waveform Display Webinar - see the new graphing technology
In this webinar you will see a demonstration of the new Virtuoso Waveform Display which is available in Virtuoso IC615. It has a powerful and intuitive graphical user interface, and provides a lot of flexibility in the displaying and post processing of simulation results. It is specifically tuned for handling large transient simulation databases to enable fast viewing, zooming and panning.
The demo will show how workspaces and assistants are used in the new graph, together with intuitive features like drag and drop, the new zoom bar, multiple selection, markers, flexible strips and sub windows, a clean interface into ADE L and XL, as well as advanced tools such as the Calculator and Eye Diagram assistant.
Register here »
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| Digital Implementation |
Cadence blog: 28 nm IC Design: The Devil Is In The Details
Smaller process technologies are enticing chip makers with bigger rewards from their end products. The shorter gate lengths at 28nm promise faster transistor speeds and less leakage power, and can double the amount of the logic that can be put into the same die area. Most importantly, however, more die on a wafer means lower per unit cost. Read more »
Cadence blog: Tortoise Versus Hare ... or How to Improve Your Time to Tapeout Using In-Design Signoff
Traditional design methodologies that have been established over the years were optimized for runtime, mostly by trading off accuracy. By reducing runtimes at points in the design where accuracy wasn't needed, a design could progress more rapidly to signoff. On the surface, this seems like a very logical approach to take. However, deeper analysis shows that this might not always enable the fastest time to tapeout. Read more »
Missed Design Con 2011? Here a couple of videos from the EDA Café.com:
- New 3D-IC Design Offering with Rahul Deokar, Cadence
- New Unified Digital Flow for 28nm Giga-gate/GHz Design with Rahul Deokar, Cadence
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| Manufacturability Signoff |
ISQED Keynote: DFM Heads in Two New Directions
By Richard Goering
Design for manufacturability (DFM) is a fairly mature discipline that you don't hear much about these days. But a recent keynote speech outlined two interesting new developments. One new twist complements traditional model-based and rules-based approaches with pattern matching, while another brings DFM further up "in design" so that problems can be avoided during IC layout and analysis.
Read more »
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| PCB and SiP design, IC packaging |
JDSU turns to Cadence Allegro technology for more automation, shorter design cycle, and lower project cost
JDSU is the leading provider of communications test and measurement solutions and optical products for a wide range of industries. One area of focus for the company's Communications Test and Measurement Group is developing instruments, systems, and software for broadband communication service providers, equipment manufacturers, and major communication users.
Putting a large, complex field programmable gate array (FPGA) on a printed circuit board (PCB) can invite a host of challenges-from unworkable pin assignments in the board layout to problems with signal integrity. So when JDSU embarked upon a new optical network tester board project with complex requirements and a tight timeline, it turned to Cadence for FPGA/PCB co-design and global routing technologies.
Download success story »
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| CDNLive!2011 EMEA - Academic Track |
CDNLive!2011 EMEA: Some highlights from this years' academic track presentations
IMMS will present a software tool for managing EDA environments and setting up project workspaces for analog/mixed-signal ASIC design teams.
RWTH Aachen and University of Heidelberg will present their results of a joint collaboration on the development of a RF-DAC based multi-standard transmitter system.
CERN will report on the development of Mixed Signal Design Kits and Workflows to improve design productivity of ASICs for applications on large scale Particle Physics experiments.
More information »
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| Education Services |
Upcoming training releases:
Please check our website or contact your local training contact for further details.
Physical Verification System v10.1 
Users will learn how to use the powerful and straightforward PVS debugging environment to locate errors and fix real problems quickly.
SystemVerilog Advanced Verification using UVM 1.0
Virtuoso v IC6.1.5 courses - out now
Virtuoso Schematic Editor v 6.1.5
Introduction to SKILL Language Programming vIC 6.1.5
... and more to come soon |
Visit Education Services at CDNLive! EMEA
Following last year´s great response, we are happy to announce the continuation of Education Services hands on demo sessions, at CDNLive! EMEA 2011:
Hands-On UVM for Beginners - understanding and controlling a UVM testbench environment
The recent release of UVM1.0 has removed the final barriers to the adoption of UVM by SystemVerilog verification engineers. In this hands-on session, we will show you the basic architecture of a UVM verification environment and give you a hands-on opportunity to define stimulus using UVM and drive this stimulus into a Design Under Test (DUT) using a pre-built UVM Verification Component (UVC).
For a detailed description and prerequisites, have a look at the event agenda
Participants have the chance to win 1 out of 3 Practical Guides to Adopting the Universal Verification Methodology (UVM). |
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